ASIC Digital Design Verification, Principal Engineer

Das ist der Job

We Are: At Synopsys, we drive the innovations that shape the way we live and connect.

Darum lohnt es sich

You are proactive, with excellent communication skills that enable you to work effectively with cross‑functional teams. Collaborating with design and architecture teams to identify and fix bugs. Driving innovation and excellence within the verification team. Collaborative team player who thrives in a dynamic environment.

The Team You’ll Be A Part Of: You will be part of a highly skilled and motivated verification team focused on delivering cutting‑edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges.

Our technology is central to the Era of Pervasive Intelligence, from self‑driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high‑performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: An enthusiastic and detail‑oriented ASIC Digital Design Engineer with a passion for cutting‑edge technology and a penchant for solving complex problems. You thrive in a collaborative environment and are adept at translating high‑level requirements into robust and efficient designs.

You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. You can work independently on complex challenges and deliver innovative solutions. Your ability to adapt quickly to new challenges and technologies ensures that you remain at the forefront of industry advancements.

What You’ll Be Doing: Designing and implementing verification environments to ensure the correctness of Interface IP protocols. Performing all tasks related to verifying a complex digital IP, including detailed test plans, functional coverage analysis, and driving coverage closure.

Mentoring and guiding junior verification engineers in best practices and methodologies. Conducting design and verification reviews and providing constructive feedback to improve overall quality and functionality. Documenting design specifications, test plans, and verification reports.

Proficiency in SystemVerilog, UVM, SVA, and other verification techniques. Strong understanding of digital design and verification concepts. Excellent problem‑solving skills and attention to detail. The Impact You Will Have: Ensuring the delivery of high‑quality, reliable ASIC designs that meet customer specifications.

Enhancing the robustness and efficiency of our verification processes and methodologies. Contributing to the successful launch of Interface IP products, impacting various industries. Improving the overall performance and functionality of Synopsys' IP offerings. Fostering a culture of continuous improvement and technical excellence.

What You’ll Need: Proficiency in digital design and verification methodologies. Experience with developing testbenches using SystemVerilog and UVM. Expertise in using advanced verification techniques. Familiarity with scripting languages such as Python or Perl for automation. Who You Are: Detail‑oriented with a strong analytical mindset.

Excellent communicator, able to convey complex technical concepts clearly. Proactive and self‑motivated, with a commitment to continuous learning. A results‑driven professional committed to delivering high‑quality work. Mentor and leader, capable of guiding and developing junior engineers.

You will have the opportunity to work alongside industry experts and contribute to the development of next‑generation technologies. #J-18808-Ljbffr