Digital Design Verification Engineer

Das ist der Job

Role Overview Design Verification Engineer with expertise in System Verilog , UVM methodology.

Darum lohnt es sich

Experience in ASIC-Memory Design methodology. DDR protocol knowledge is preferable. This engineer shall collaborate with architects and designers to meet performance and reliability requirements. Mixed signal verification.

Must Have Master’s degree in Electrical Engineering, Computer Engineering. 5+ years of experience in ASIC/DRAM/NAND/NOR Memory design verification Strong skills in SystemVerilog and UVM methodology. Cadence tool chain knowledge (Virtuoso, ADE, Xcelium, Simvision) or equivalent Synopsys verification tool chain.

Problem Solving and Communication skills. Responsibilities Develop and maintain UVM-based verification environments. Create test plans, testbench and stimuli. Create analogue blocks and memory models. Execute both block and system levels verification. Simulate and debug using Cadence/Synopsys tools for design inspection.

Verify and validate DDR4/DDR5 command user interface of the memory. Verify and validate internal Memory core. RTL coverage and gate level simulation with SDF back-annotation for timing closure checks. Run regression tests reporting results to design engineer. Collaborate with design engineers.

Your profile Master’s degree in Electrical Engineering, Computer Engineering. 5+ years of experience in ASIC/DRAM/NAND/NOR Memory design verification Strong skills in SystemVerilog and UVM methodology Experience in DDR4, LPDDR4/5, or DDR5 is preferrabl