Digital Design & Verification (RTL + UVM + Microarchitecture)

ph3Digital Design Verification (RTL + UVM + Microarchitecture) /h3 pWe are searching for Senior Digital Engineers with strong RTL and Verification expertise to join a deep-tech compute architecture team.

The role involves hybrid responsibilities across microarchitecture, RTL development, DV environments and subsystem integration. /p h3Responsibilities /h3 ul liDevelop RTL for compute subsystems, controllers, datapaths and interfaces /li liContribute to microarchitecture definition and technical reviews /li liBuild UVM-based verification environments and test plans /li liDrive functional coverage, constrained-random testing and debug /li liSupport FPGA bring-up and silicon validation activities /li liCollaborate with physical design, architecture and mixed-signal teams /li /ul h3Requirements /h3 ul liStrong background in RTL coding (SystemVerilog/Verilog) /li liSolid experience with UVM and modern DV methodologies /li liKnowledge of SoC integration, buses, protocols (AXI/APB) /li liExposure to FPGA, DFT, CDC/RDC, linting and subsystem verification /li liAbility to work across design +

verification flows with technical ownership /li /ul /p