Senior Digital Design and Verification Engineer

ppZürich, Switzerlandbr/Seniority: 6 years /p pOwn the design and verification of part of our digital IP portfolio that wraps and integrates our compute-in-memory technology(ComputeRAM®): clean, synthesis-ready SystemVerilog RTL, plus UVM environments that reach coverage closure and de-risk silicon. You’ll specify and build register/bus interfaces, DMA, and control logic.

Expect tight collaboration with custom design, backend, and software teams to hit PPA, coverage, and time-to-tapeout simultaneously. /p h3What you’ll do /h3 ul liImplement RTL: memory-mapped control blocks, AXI/AHB/APB bridges, FIFOs/scoreboards, arbiters, DMA, and datapaths; write synthesis-friendly code with a clear reset/CDC strategy. /li liExtreme optimization for power, with a power-driven mindset and approach to design /li liDevelop UVM testbenches (agents, sequencers, predictors, scoreboards); drive constrained-random + directed testing; close coverage (func/code/assertion). /li liGLS: run gate-level sims with SDF for critical paths; support FPGA prototypes for early HW/SW bring-up. /li liDocumentation specs: write IP/user guides, register maps, programming models; contribute reusable UVM components and regression infrastructure for the team. /li /ul h3Outcomes (first 18 months)

/h3 ul liTape-in of one or more IPs (or a subsystem) with coverage goals met (functional/code/assertion) and lint/CDC/RDC clean sign-off packages. /li liDemonstrated GLS/SDF pass on the IP’s top-risk paths and correlation to FPGA results; Achieve sign-off quality. /li liA reusable UVM kit (agents/sequences/scoreboards) and CI scripts that cut regression time and raise pass-rate stability across projects. /li /ul h3Requirements /h3 ul li5+ years in digital design or verification for ASIC; strong SystemVerilog RTL and basic understanding of UVM /li liHands-on experience with either RISC-V or ARM architectures, either as a system-level integrator or as a designer. /li liKnowledge of synthesis basics and how RTL choices impact timing/power/area /li liClear technical communication, ability to work with structured specs, and habit of turning one-off designs into reusable components. /li /ul

h3Nice to have /h3 ul liExperience verifying memory-adjacent IP (SRAM controllers/periphery, MBIST/scan integration) and power-aware/UPF simulation flows. /li liAMBA (AXI/AHB/APB) protocols, clock/reset schemes, CDC handshakes, FIFOs, arbiters; comfortable writing SVAs. /li liGLS proficiency (SDF back-annotation), familiarity with FPGA bring-up and HW/SW test harnesses. /li liPython/Tcl for stimulus generation, log parsing, coverage triage /li liBackground in AI/DSP accelerators or quantized dataflows (helpful context for CxR use-cases). /li /ul /p