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Key Responsibilities Lead RTL development for complex digital modules and subsystem-level designs Integrate IP blocks into larger SoC architectures and ensure system-level consistency Run and interpret design quality checks including Lint, CDC, and RDC Support synthesis and help guide designs towards optimal timing, area, and power Participate in debug, simulation, and functional verification activities Work closely with verification teams, including environments using UVM methodologies Contribute to architecture discussions, design reviews, and release/sign-off activities Help improve design flow efficiency and engineering practices across the team Required Skills & Experience Extensive background (10+ years) in RTL design and SoC or subsystem integration Strong understanding of digital logic design and microarchitecture principles Experience with industry synthesis tools such as Synopsys Design Compiler or Cadence Genus Hands‑on experience with Lint, CDC, and RDC analysis flows Solid understanding of simulation and verification approaches, including UVM concepts Comfortable with scripting (TCL, Python or similar) to support automation and flow work Nice to Have Exposure to SoC integration frameworks such as Magillem Interest in modern productivity approaches, including the use of AI/LLM tools in engineering workflows Experience with large-scale or high-performance SoC designs #J-18808-Ljbffr We are supporting the development of a complex digital SoC environment and are looking for a highly experienced Senior RTL Design Engineer with strong subsystem and integration expertise.
The role sits at the intersection of RTL development, SoC integration, and design quality assurance, with responsibility for ensuring that digital blocks integrate correctly into larger system architectures and meet strict functional and timing requirements.
