Das ist der Job
Strong skills in SystemVerilog and UVM methodology.
Darum lohnt es sich
Role Overview Design Verification Engineer with expertise in System Verilog, UVM methodology, ASIC-Memory Design methodology, and DDR protocol knowledge. The engineer collaborates with architects and designers to meet performance and reliability requirements, focusing on mixed signal verification.
Requirements Master’s degree in Electrical Engineering or Computer Engineering. 5+ years of experience in ASIC/DRAM/NAND/NOR memory design verification. Cadence tool chain knowledge (Virtuoso, ADE, Xcelium, Simvision) or equivalent Synopsys verification tool chain. Problem solving and communication skills.
Programming and scripting skills (Linux commands, Tcl, Python). Responsibilities Develop and maintain UVM-based verification environments. Create test plans, testbench, and stimuli. Create analogue blocks and memory models. Execute both block and system level verification. Simulate and debug using Cadence/Synopsys tools for design inspection.
Verify and validate DDR4/DDR5 command user interface of the memory. Verify and validate internal memory core. Perform RTL coverage and gate level simulation with SDF back‑annotation for timing closure checks. Run regression tests and report results to design engineers. Collaborate with design engineers.
Ideal Fit Experience in mixed signal verification for memory design. Experience with DDR4, LPDDR4/5, or DDR5. Cadence verification tool chain experience including Virtuoso, ADE, Xcelium, Simvision. Strong problem solving attitude. #J-18808-Ljbffr
