Darum lohnt es sich
Extending our international team, we are looking for an experienced Digital Design Engineer.
Job Description Define architecture of digital blocks according to customer specification for ASIC and FPGA Designs Responsibility for RTL design (VHDL, Verilog) of digital blocks and their system level integration Close cooperation with RTL2GDS flow experts to optimize digital blocks and support block implementation Support and drive chip and block level functional verification Implement and maintain regression setups for verification Create verification plans and develop verification environments based on Unified Verification Methodology (UVM) Support product qualification, testing and ramp-up Develop methodology, implement flow and methodology enhancements Actively support Project Management Requirements Bachelor’s/Master’s Degree in Electrical Engineering, Information Technology or a related field At least 5+ years of experience in digital design and verification Strong knowledge of hardware description languages (VHDL, Verilog and SystemVerilog) Experience in SoC design Experience in major IPs and SoC protocols (e.g.
AHB/APB, Arm Cortex M3) Experience in developing verification methodologies and infrastructure for test benches Experience in writing test cases in Verilog and C Experience in scripting for design automation (e.g.
Python, Perl, TCL) Knowledge of synthesis constraints (SDC) and UPF Understanding of UVM/OVM concepts and usage Experience in functional verification and creating test concepts and verification environments Self‑driven and hands‑on way of working Strong analytical and solution‑oriented thinking Good written and oral communication skills in English Location: Dresden, Germany; Duisburg, Germany Employment Type: Full‑time (up to 40 hours per week) #J-18808-Ljbffr
