Darum lohnt es sich
Benefits Role Overview
• Design Verification Engineer with expertise in System Verilog, UVM methodology.
• Experience in ASIC-Memory Design methodology.
• DDR protocol knowledge is preferable.
• This engineer shall collaborate with architects and designers to meet performance and reliability requirements.
• Mixed signal verification.
Must Have
• Master’s degree in Electrical Engineering, Computer Engineering.
• 5+ years of experiencein ASIC/DRAM/NAND/NOR Memory design verification
• Strong skills inSystemVerilogandUVMmethodology.
• Cadence tool chain knowledge (Virtuoso, ADE, Xcelium, Simvision) or equivalent Synopsys verification tool chain.
• Problem Solving and Communication skills.
Responsibilities
• Develop and maintainUVM-based verification environments.
• Create test plans, testbench and stimuli.
• Create analogue blocks and memory models.
• Execute both block and system levels verification.
• Simulate and debug using Cadence/Synopsys tools for design inspection.
• Verify and validateDDR4/DDR5 command user interface of the memory.
• Verify and validate internal Memory core.
• RTL coverage and gate level simulation with SDF back-annotation for timing closure checks.
• Run regression tests reporting results to design engineer.
• Collaborate with design engineers.
Your profile
• Master’s degree in Electrical Engineering, Computer Engineering.
• 5+ years of experiencein ASIC/DRAM/NAND/NOR Memory design verification
• Strong skills inSystemVerilogandUVMmethodology
• Experience in DDR4, LPDDR4/5, or DDR5 is preferrable.
• Cadence tool chain knowledge (Virtuoso, ADE, Xcelium, Simvision) or equivalent Synopsys verification tool chain.
Ideal fit
• Asic design and mixed signal verification knowledgepreferably in memory design
• System Verilog and UVM methodology experience.
• Cadence verification tool chain experience (Virtuoso Schematic Entry, ADE, Xcelium, Simvision)
• Programming and scripting skill (linux commands, tcl, python)
• Problem solving attitude.
